Multilayer PCB Design – Impact of Vias on High Frequency Signal Transmission

First, the basic concept of vias

Through-hole (via) is an important part of the multilayer PCB, drilling costs usually account for 30% to 40% of the cost of PCB board. Simply put, every hole on the PCB can be called a hole.

From the role of point of view, over the hole can be divided into two categories: one is used as an electrical connection between the layers; the second is used as a device fixed or positioning.

If the process from the process, these holes are generally divided into three categories, namely, blind holes (blind via), buried holes (buried via) and through holes (through via).

Blind vias are located on the top and bottom surfaces of the printed wiring board, with a certain depth, for the surface layer of the line and the connection of the inner layer of the line below, the depth of the hole is usually no more than a certain ratio (aperture diameter).

Buried holes are connection holes located in the inner layer of the printed wiring board which do not extend to the surface of the board.

The above two types of holes are located in the inner layer of the circuit board, lamination before the use of through-hole molding process to complete, in the process of over-hole formation may also overlap well several inner layers.

The third type is called through-hole, this hole through the entire board, can be used to realize the internal interconnection or as a component mounting holes. Because the through-hole is easier to realize in the process, the cost is lower, so the vast majority of printed circuit boards use it, rather than the other two types of through-hole. The following vias are considered as through-holes unless otherwise specified.

From the design point of view, a through-hole consists of two main parts, one is the center of the drill hole (drill hole), and the second is the pad area around the drill hole.

The size of these two parts determines the size of the hole. Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the better the hole, so that the board can leave more wiring space, in addition, the smaller the hole, the smaller its own parasitic capacitance is also more suitable for high-speed circuits.

But the reduction of hole size at the same time brought about by the increase in cost, and the size of the hole can not be unlimited reduction, it is subject to drilling (drill) and plating (plating) and other technological constraints: the smaller the hole, drilling takes longer, but also the more likely to deviate from the center of the position; and when the depth of holes more than the diameter of the hole when the 6 times, it is not possible to ensure that the walls of the holes can be uniformly plated with copper.

For example, if a normal 6-layer PCB board thickness (through-hole depth) for 50Mil, then, under normal conditions, PCB manufacturers can provide the minimum diameter of the drilled holes can only be up to 8Mil With the development of laser drilling technology, the size of the drilled holes can also be smaller and smaller, the general diameter of less than or equal to 6Mils of the through-hole, we will be called the micro-hole.

Microvias are often used in HDI (High Density Interconnect) designs. Microvia technology allows vias to be placed directly on the pads (Via-in-pad), which greatly improves circuit performance and saves wiring space.

Vias appear as impedance discontinuities in the transmission line as breakpoints, which can cause signal reflections.

Generally, the equivalent impedance of the vias is about 12% lower than that of the transmission line, for example, a 50-ohm transmission line will have a 6-ohm reduction in impedance when passing through the vias (specific and vias of the size of the board thickness is also relevant, not an absolute reduction).

But because of the impedance discontinuity caused by the reflection of the hole is actually minimal, the reflection coefficient is only: (44-50)/(44+50)=0.06, the problem generated by the hole is more focused on the parasitic capacitance and inductance of the impact.

Second, the parasitic capacitance and inductance of the perforation

Through-hole itself there is a parasitic stray capacitance, if the known through-hole in the pavement layer on the soldermask diameter of D2, through-hole pad diameter of D1, the thickness of the PCB board for the T, the board substrate dielectric constant of ε, the size of the parasitic capacitance over the hole is approximated: C = 1.41εTD1 / (D2 – D1)

The main effect of the parasitic capacitance of the vias on the circuit is to lengthen the rise time of the signal, reducing the speed of the circuit.

For example, for a thickness of 50Mil PCB board, if the use of the over-hole pad diameter of 20Mil (drilling diameter of 10Mils), soldermask diameter of 40Mil, then we can approximate the formula above to calculate the parasitic capacitance of the over-hole is roughly: C = 1.41×4.4×0.050×0.020 / (0.040 – 0.020) = 0.31pF The amount of change in rise time due to this part of the capacitance is roughly T10-90 = 2.2C(Z0/2) = 2.2×0.31x(50/2) = 17.05ps

From these values, it can be seen that although the utility of slowing down the rise delay caused by the parasitic capacitance of a single via is not very obvious, if the alignment uses multiple via holes for switching between layers several times, multiple via holes will be used, and the design will have to be carefully considered.

In practice, parasitic capacitance can be reduced by increasing the distance between the via and the copper-laying area (Anti-pad) or by reducing the diameter of the pad.

The parasitic capacitance of the vias also has parasitic inductance, and in the design of high-speed digital circuits, the parasitic inductance of the vias is often more harmful than the parasitic capacitance.

Its parasitic series inductance weakens the contribution of the bypass capacitor and diminishes the filtering utility of the entire power system. We can use the following empirical formula to simply calculate an approximate parasitic inductance of the over-hole: L = 5.08h [ln (4h/d) +1] where L refers to the inductance of the over-hole, h is the length of the over-hole, d is the diameter of the center hole.

As can be seen from the equation, the diameter of the hole has a small effect on the inductance, while the largest effect on the inductance is the length of the hole. Still using the above example, you can calculate the inductance of the hole: L = 5.08×0.050 [ln (4×0.050/0.010) +1] = 1.015nH If the rise time of the signal is 1ns, then the equivalent impedance is: XL = πL/T10-90 = 3.19Ω.

Such an impedance in the passage of high-frequency current can not be ignored, in particular, note that the bypass capacitor in the connection between the power supply layer and the ground layer needs to pass through the two vias, so that the parasitic inductance of the vias will increase exponentially.

How to use vias

Through the above analysis of the parasitic characteristics of the over-hole, we can see that in high-speed PCB design, the seemingly simple over-hole will often bring a great deal of negative effects to the circuit design. In order to minimize the parasitic effects of vias, you can try to do as much as possible in the design:

1. From the cost and signal quality considerations, choose a reasonable size of the over-hole size. If necessary, you can consider the use of different sizes of vias, such as for power or ground vias, you can consider using a larger size to reduce impedance, while for the signal alignment, you can use a smaller vias. Of course, as the size of the hole is reduced, the corresponding cost will increase.

2. The above discussion of the two formulas can be derived from the use of thinner PCB board is conducive to reducing the two parasitic parameters of the over-hole.

3. PCB board signal alignment as far as possible not to change layers, that is, try not to use unnecessary holes.

4. Power and ground pins should be played near the hole, the shorter the lead between the hole and the pin, the better. Consider playing multiple vias in parallel to reduce the equivalent inductance.

5. Place some grounded vias near the vias of the signal layer changeover in order to provide the nearest circuit for the signal. You can even place some extra grounded vias on the PCB board.

6. For high density and high speed PCBs, consider using micro vias.